Annals of the Assembly for International Heat Transfer Conference 13

ISBN 1-56700-225-0 / CD 1-56700-226-9

Year 2006

A. Shah
University of California, Berkeley, USA

Van Carey
University of California at Berkeley, 6124a Etcheverry Hall, Berkeley, CA 94720, USA

C. Bash
Hewlett Packard Laboratories, Palo Alto, USA

C. Patel
Hewlett Packard Laboratories, Palo Alto, USA

Computer networks have traditionally followed a sequential path of instruction from the chip to the data center. However, while network scalability has long been a subject of interest in the computer science community, only limited information is available regarding the thermofluidic scalability of computer systems. This paper attempts to fill this gap of knowledge by examining the energy efficiency and corresponding thermal management requirements at the different levels of computation (chip, system, rack, data center). Through a survey of the available literature and prototype measurements, we find that the coefficient of performance (COP) of thermal management systems vary across the different computational levels by as much as a factor of 30. To explain this behavior, the different inefficiencies that govern the thermal management systems at each length scale are examined. The impacts of these inefficiencies are quantified in terms of an exergy loss, and the thermodynamic performance is then normalized per unit of information processed. The resulting figure-of-merit suggests that the compounding of thermofluidic inefficiencies at the larger length scales tends to outweigh any computational benefits, so much so that the energy efficiency per unit instruction typically drops by over an order of magnitude from the chip to the data center. Thus, in addition to low-power microprocessors - which have long been an area of research - we emphasize the need for energy-efficient systems and data centers as a means to combating thermal management problems.

ENR-13 pages DOI: 10.1615/IHTC13.p24.130 Download article

Article price - $35.00

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