Annals of the Assembly for International Heat Transfer Conference 13

ISBN 1-56700-225-0 / CD 1-56700-226-9

Year 2006

P. Wang
Department of Mechanical Engineering, University of Maryland, Maryland, USA

Avram Bar-Cohen
Laboratory of the Thermal Management of Electronics, Department of Mechanical Engineering, University of Minnesota, Minneapolis, MN 55455; and Department of Mechanical Engineering, University of Maryland, College park, MD 20742, USA

B. Yang
Department of Mechanical Engineering, University of Maryland, Maryland, USA

Driven by shrinking feature sizes, microprocessor hotspots on silicon chips - with their associated high heat flux and sharp temperature gradients - have emerged as the primary "driver" for thermal management of today's IC technology. Solid state thermoelectric microcoolers, fabricated and judiciously distributed on the back surface of the silicon chip, offer great promise for reducing the severity of on-chip hotspots. In this paper the results of a systematic, three-dimensional, numerical thermal-electrical coupled analysis of the temperature field generated by an array of on-chip silicon thermoelectric microcoolers are presented. Attention is focused on the hotspot temperature reductions associated with variations in microcooler number, microcooler sizes, microcooler spacing, chip thickness, silicon doping concentration and the parasitic Joule heating effect from electrical contact resistance. These results suggest that a 3×3 microcooler (70μm×70μm) array on the back surface of silicon chip could remove 80% of the temperature rise produced by a 70μm×70μm hotspot with a heat flux of 680W/cm².

CND-09 pages DOI: 10.1615/IHTC13.p27.90 Download article

Article price - $35.00

<< Previous article   Next article >>