New Chip Scale Package (CSP) designs increase silicon die area to package area but at increased cost and a different footprint to existing Peripheral leaded packages such as Small Outline Integrated Circuit (SOIC) packages. These CSP packages require a redesign of the handling equipment, which is costly. The volume package typically used is SOIC and it will continue in use for many years. By utilising the existing SOIC gull wing footprint and redesigning around this constraint more silicon can be placed in existing packages. One of the principal issues involved is understanding the stresses and using this knowledge to develop solutions to overcome the stresses. The current SOIC packages have been developed and tested in use over several years and have proved their manufacturability reliability and robustness in use. It is proposed to use the current SOIC package as a benchmark and develop ways of measuring Stress levels. The existing strain gauges developed on silicon will provide the method for benchmarking but require proper calibration and translation into stress. New and existing package designs can then be compared with this model and decisions made on the viability of these designs. Finite element analysis models will be developed and these models checked against the actual measurements to realise models that will closely simulate what happens in the real packages.